A time domain filter circuit is devised to remove a pulse having a pulse width being shorter than a predetermined time, from pulses obtained by performing a level discrimination on input signals, so as to prevent noise. As a typical conventional art, for example, a circuit disclosed in Japanese Published Unexamined Patent Publication No. 152116/1986 (Tokukaisho 61-152116, published on Jul. 10, 1986) has been known. FIG. 5 is a block diagram showing an FDD read-data reproducing device 2 including a time domain filter 1 devised in accordance with the conventional art. Further, FIG. 6 is a timing chart for explaining an operation of the circuit shown in FIG. 5, and each signal name corresponds to each of nodes `a` through `i` of FIG. 5.
Reproduction signals, which are reproduced in a reproducing head 3 are inputted to a signal processing circuit 4 as differential signals having opposite phases, are subjected to operations of amplification, filtering, and differentiation, and are inputted to a comparing circuit 5. For a simple explanation, regarding a signal of node `a`, FIG. 5 shows only one of the differential signals that is inputted to one of inputs of the comparing circuit 5; however, in an actual arrangement, a signal having a phase being opposite to a node `a` signal is inputted to the other input of the comparing circuit 5. An input signal (node `a`) to the comparing circuit 5 has waveform distortion of saddling SD due to the differentiation. Due to such waveform distortion, an error data ED appears in the output (node `b`) of the comparing circuit 5. The error data ED is removed in the time domain filter 1 in the next step as follows:
The time domain filter 1 schematically consists of an exclusive OR 6, a monostable multivibrator 7, and a D-type flip-flop 8. The output (node `b`) of the comparing circuit 5 is inputted to one of inputs of the exclusive OR circuit 6 and to a data input D of the D-type flip-flop 8. An output signal (node `h`) of the time domain filter 1, that also serves as a Q output of the D-type flip-flop 8, is inputted to the other input of the exclusive OR circuit 6.
Therefore, when a signal inputted to the time domain filter 1 is changed, the output (node `c`) of the exclusive OR circuit 6 is changed to "H" so as to detect a change of the input signal. The signal acts as a trigger so as to operate the monostable multivibrator 7. After a predetermined time W1 elapses, an "L" pulse (node `g`) is inputted to a clock of the D-type flip-flop 8 so as to change the Q output of the D-type flip-flop 8. Namely, the circuit construction is arranged as follows: after the time W1 elapses since an input signal (node `b`) to the time domain filter 1 has been changed, an output signal (node `h`) of the time domain filter 1 is changed.
Here, the following explanation describes an operation of the monostable multivibrator 7 in detail. The output of the exclusive OR circuit 6 is connected to the base of an NPN transistor 11, the collector of the NPN transistor 11 is connected to the base of an NPN transistor 12 and to a high-level power supply via a resistance 13, and the emitter of the NPN transistor 11 is grounded via a resistance 14.
The emitter of the NPN transistor 12 is grounded via a constant-current power supply 15 and is connected to a non-inverse input end of the comparing circuit 16, and the collector of the NPN transistor 12 is connected to the high-level power supply. A capacitor 17 is connected in parallel with the NPN transistor 12. A reference voltage vref is applied from a reference voltage source supply 18 to an inverse input end of the comparing circuit 16.
Therefore, when the base potential of the NPN transistor 11 is "L", the NPN transistor 11 is interrupted, a base potential (node `e`) of the NPN transistor 12 is pulled up to "H" in the resistance 13, and the NPN transistor 12 is brought into conduction so as to supply current drawn by the constant-current power supply 15 and to cause a short circuit between terminals, thereby discharging the capacitor 17. At this time, an emitter potential (node `f`) of the NPN transistor 12, namely, a voltage at the non-inverse input end of the comparing circuit 16 is at a high level.
Meanwhile, when the base of the NPN transistor 11 is "H", the NPN transistor 11 is brought into conduction, and the base potential of the NPN transistor 12 becomes "L" due to a voltage drop caused by the collector current. As a result, the NPN transistor 12 is interrupted, and when current is drawn by the constant-current power supply 15, the charging of the capacitor 17 begins. At this time, an emitter potential (node `f`) of the NPN transistor 12, namely, a voltage at the non-inverse input end of the comparing circuit 16 is reduced by the charging at a speed determined by a capacitance of the capacitor 17 and a current value of the constant-current power supply 15. After the time W1 elapses, the voltage is reduced to the reference voltage vref or less, the output (node `g`) of the comparing circuit 16 becomes "L", and the clock is inputted to the D-type flip-flop 8.
As described above, in the monostable multivibrator 7, a rise of the output of the exclusive OR circuit 6 acts as a trigger, and after the predetermined time W1 elapses, the "L" level is outputted from the output of the comparing circuit 16 to the clock input of the D-type flip-flop 8. When the "L" clock is inputted to the D-type flip-flop 8, the Q output (node `h`) of the D-type flip-flop 8 becomes equal to the input signal (node `b`).
Hence, as in the case of the saddling SD of the input signal (node `b`), even when an output of the comparing circuit 5 is changed at an interval being shorter than the time W1, the error data ED is reset to the "H" level before an emitter potential (node `f`) of the NPN transistor 12 is reduced to the reference voltage vref, so that the clock is not inputted to the D-type flip-flop 8 so as to remove the error data ED. Namely, regarding the saddling SD, a signal varies at an interval being shorter than the time W1, the effect thereof is eliminated so as to prevent the occurrence of the error data ED.
The Q output (time domain filter output) of the D-type flip-flop 8 is inputted to a read-data output pulse width setting circuit 9, is shaped into a predetermined pulse width W2 having a change of an output of the time domain filter 1 as a trigger, and is outputted as read data (node The time domain filter 1 of the above conventional art makes it possible to remove the effect of waveform distortion such as the saddling SD. However, when a high-frequency noise N is inputted, a pulse interval of the read data becomes shorter than the time W1. The high-frequency noise N appears upon reading a non-recording medium.
Namely, as shown in FIG. 6, at a time t0 or later, immediately after the Q output (node `h`) of the D-type flip-flop 8 is changed, the output (node `b`) of the comparing circuit 5 is changed, so that the charging is resumed before the capacitor 17 is fully discharged (while potentials of the nodes `e` and `f` are not sufficiently raised), resulting in an output at an interval being shorter than the time W1 (node `h`). For example, when the node `e` has a parasite capacitance of 1 pF and the resistance 13 has a resistance value of 10 k.OMEGA., a time constant for changing the node `e` to "H" is 10 ns. When the output of the comparing circuit 5 is changed at less than 10 ns, the aforementioned malfunction occurs.
For this reason, even when the time W1 is set at 2 .mu.s, which is determined by the capacitance of the capacitor 17, the current value of the constant-current power supply 15, and the reference voltage vref, the output of the time domain filter 1 is outputted at an interval being shorter than the predetermined width (2 .mu.s).
As described above, regarding the conventional time domain filter 1, when another signal is inputted when the capacitor 17 is not fully discharged in the monostable multivibrator 7, an interval of an output signal is reduced. Hence, for example, in the FDD reading circuit, when the output interval of the time domain filter 1 is reduced, a pulse interval of the read-data output pulse (node `i`) is reduced accordingly, so that a reading error may occur during an inspection of the FDD or in a state connection is made to a personal computer and the like.